Glossary

Term Introduced in
__device__ Part 2 — 2.1 A first kernel
__global__ Part 2 — 2.1 A first kernel
alignment Part 3 — 3.3 Coalescing
atomic Part 5 — 5.2 Making the cooperation local
bank Part 5 — 5.5 Banks and bank conflicts
bank conflict Part 5 — 5.5 Banks and bank conflicts
block Part 2 — 2.2 Threads, Blocks, and Grids
broadcast Part 5 — 5.5 Banks and bank conflicts
bytes in flight Part 6 — 6.2 Bytes in flight
Cooperative Thread Array Part 2 — 2.2 Threads, Blocks, and Grids
cubin Part 2 — 2.5 What nvcc actually does
CUDA toolkit Part 1 — 1.5 The toolchain
deadlock Part 2 — 2.2 Threads, Blocks, and Grids
device Part 1 — Part 1 — Introduction
device pointer Part 1 — 1.3 Moving data
divergence Part 3 — 3.2 Divergence
DRAM Part 1 — 1.4 The memory hierarchy
driver Part 1 — 1.5 The toolchain
driver API Part 1 — 1.5 The toolchain
execute Part 3 — 3.1 Single instruction, multiple threads
fatbin Part 2 — 2.5 What nvcc actually does
GDDR Part 1 — 1.4 The memory hierarchy
grid Part 2 — 2.2 Threads, Blocks, and Grids
HBM Part 1 — 1.4 The memory hierarchy
host Part 1 — Part 1 — Introduction
issue Part 3 — 3.1 Single instruction, multiple threads
kernel Part 2 — 2.1 A first kernel
kernel launch Part 2 — 2.1 A first kernel
L1 cache Part 1 — 1.4 The memory hierarchy
L2 cache Part 1 — 1.4 The memory hierarchy
lane Part 3 — 3.1 Single instruction, multiple threads
latency Part 4 — 4.1 Pipelining and latency hiding
memory hierarchy Part 1 — Pinned memory
memory-bound Part 3 — Caches and cachelines
MIMD Part 3 — 3.1 Single instruction, multiple threads
Nsight Compute Part 3 — 3.4 Profiling
occupancy Part 4 — 4.2 Occupancy
pinned memory Part 1 — Pinned memory
pipelined Part 4 — 4.1 Pipelining and latency hiding
predication Part 3 — † SIMD and SIMT
PTX Part 2 — 2.5 What nvcc actually does
ptxas Part 2 — 2.5 What nvcc actually does
register Part 1 — 1.4 The memory hierarchy
register spill Part 4 — 4.2 Occupancy
request Part 3 — 3.3 Coalescing
resident Part 4 — 4.1 Pipelining and latency hiding
retire Part 3 — 3.1 Single instruction, multiple threads
SASS Part 2 — 2.5 What nvcc actually does
sector Part 3 — 3.3 Coalescing
shared memory Part 5 — 5.3 Shared memory
SIMD Part 3 — 3.1 Single instruction, multiple threads
SIMT Part 3 — 3.1 Single instruction, multiple threads
spill Part 6 — __launch_bounds__
SRAM Part 1 — 1.4 The memory hierarchy
stall Part 3 — 3.1 Single instruction, multiple threads
streaming multiprocessor Part 1 — 1.4 The memory hierarchy
strided access Part 3 — Strided memory access
sub-partition Part 4 — Why switching warps is free
tagging Part 5 — 5.8 Recap
tensor memory Part 1 — 1.4 The memory hierarchy
thread coarsening Part 6 — 6.3 Thread coarsening
thread-block cluster Part 2 — † Thread block clusters
throughput Part 4 — 4.1 Pipelining and latency hiding
unified addressing Part 1 — † Unified addressing
unified memory Part 1 — † Unified addressing
warp Part 3 — 3.1 Single instruction, multiple threads
wave Part 2 — 2.3 Automatic scaling
wavefront Part 3 — 3.1 Single instruction, multiple threads
write-through Part 5 — 5.8 Recap